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M-8870 DTMF Receiver
* * * * * * * *
Low power consumption Adjustable acquisition and release times Central office quality and performance Power-down and inhibit modes (-02 only) Inexpensive 3.58 MHz time base Single 5 volt power supply Dial tone suppression Applications include: telephone switch equipment, remote data entry, paging systems, personal computers, credit card systems
The M-8870 is a full DTMF Receiver that integrates both bandsplit filter and decoder functions into a single 18-pin DIP or SOIC package. Manufactured using CMOS process technology, the M-8870 offers low power consumption (35 mW max) and precise data handling. Its filter section uses switched capacitor technology for both the high and low group filters and for dial tone rejection. Its decoder uses digital counting techniques to detect and decode all 16 DTMF tone pairs into a 4-bit code. External component count is minimized by provision of an on-chip differential input amplifier, clock generator, and latched tri-state interface bus. Minimal external components required include a low-cost 3.579545 MHz color burst crystal, a timing resistor, and a timing capacitor.
Figure 1 Pin Connections The M-8870-02 provides a "power-down" option which, when enabled, drops consumption to less than 0.5 mW. The M-8870-02 can also inhibit the decoding of fourth column digits (see Table 5).
Figure 2 Block Diagram
Teltone Corporation, 22121-20th Avenue SE, Bothell, WA 98021-4408 U.S.A 40-406-00011, Rev. E
Phone: 800-426-3926 or 425-487-1515 Fax: 425-487-2288 E-mail: info@teltone.com Internet: www.teltone.com
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M-8870 Functional Description
M-8870 operating functions (see Figure 2) include a bandsplit filter that separates the high and low tones of the received pair, and a digital decoder that verifies both the frequency and duration of the received tones before passing the resulting 4-bit code to the output bus. Filter The low and high group tones are separated by applying the dual-tone signal to the inputs of two 6th order switched capacitor bandpass filters with bandwidths that correspond to the bands enclosing the low and high group tones. The filter also incorporates notches at 350 and 440 Hz, providing excellent dial tone rejection. Each filter output is followed by a single-order switched capacitor section that smooths the signals prior to limiting. Signal limiting is performed by high-gain comparators provided with hysteresis to prevent detection of unwanted low-level signals and noise. The comparator outputs provide full-rail logic swings at the frequencies of the incoming tones. Decoder The M-8870 decoder uses a digital counting technique to determine the frequencies of the limited tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm is used to protect against tone simulation by extraneous signals (such as voice) while tolerating small frequency variations. The algorithm ensures an optimum combination of immunity to talkoff and tolerance to interfering signals (third tones) and noise. When the detector recognizes the simultaneous presence of two valid tones (known as "signal condition"), it raises the Early Steering flag (ESt). Any subsequent loss of signal condition will cause ESt to fall. Steering Circuit Before a decoded tone pair is registered, the receiver checks for a valid signal duration (referred to as "character-recognition-condition"). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes VC (see Figure 2) to rise as the capacitor discharges. Provided that signal condition is maintained (ESt remains high) for the validation period (tGTF), VC reaches the threshold (VTSt) of the steering logic to register the tone pair, thus latching its corresponding 4-bit code (see Table 3) into the output latch. At this point, the GT output is activated and drives VC to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the "delayed steering" output flag (StD) goes high, signaling that a received tone pair has been registered. The contents of the output latch are made available on the 4-bit output bus by raising the three-state control input (OE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropouts) too short to be considered a valid pause. This capability, together with the ability to select the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.
Figure 4 Single-Ended Input Configuration Guard Time Adjustment Where independent selection of signal duration and interdigit pause are not required, the simple steering circuit of Figure 3 is applicable. Component values are chosen according to the formula: tREC = tDP + tGTP tGTP 0.67 RC The value of tDP is a parameter of the device and tREC is the minimum signal duration to be recognized by the receiver. A value for C of 0.1 F is recommended for most applications, leaving R to be selected by the designer. For example, a suitable value of R for a tREC of 40 ms would be 300 k. A typical circuit using this steering configuration is shown in Figure 4. The timing requirements for most telecommunication applications are satisfied with this circuit. Different steering arrangements may be used to select independently the guard times for tone-present (tGTP) and tone-absent (tGTA). This may be necessary to meet system specifications that place both accept and reject limits on both tone duration and interdigit pause.
Figure 3 Basic Steering Circuit
Teltone Corporation, 22121-20th Avenue SE, Bothell, WA 98021-4408 U.S.A 40-406-00011, Rev. E
Phone: 800-426-3926 or 425-487-1515 Fax: 425-487-2288 E-mail: info@teltone.com Internet: www.teltone.com
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M-8870
Table 1 Pin Functions
Pin 1 2 3 4 5 6 7 8 9 10 11 - 14 Name IN+ INGS VREF INH* PD* OSC1 OSC2 VSS OE Q1, Q2, Q3, Q4 StD Description
Non-inverting input Connections to the front-end differential amplifier. Inverting input Gain select. Gives access to output of front-end amplifier for connection of feedback resistor. Reference voltage output (nominally VDD/2). May be used to bias the inputs at mid-rail. Inhibits detection of tones representing keys A, B, C, and D. Power down. Logic high powers down the device and inhibits the oscillator. Internal pulldown. Clock input 3.579545 MHz crystal connected between these pins completes the internal oscillator. Clock output Negative power supply (normally connected to 0 V). Tri-statable output enable (input). Logic high enables the outputs Q1 - Q4. Internal pullup. Tri-statable data outputs. When enabled by OE, provides the code corresponding to the last valid tone pair received (see Table 5). 15 Delayed steering output. Presents a logic high when a received tone pair has been registered and the output latch is updated. Returns to logic low when the voltage on St/GT falls below VTSt. 16 ESt Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. 17 St/GT Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time constant, and its state is a function of ESt and the voltage on St. (See Figure 7). 18 VDD Positive power supply. (Normally connected to +5V.) * -02 only. Connect to VSS for -01 version
Guard time adjustment also allows the designer to tailor system parameters such as talkoff and noise immunity. Increasing tREC improves talkoff performance, since it reduces the probability that tones simulated by speech will maintain signal condition long enough to be registered. On the other hand, a relatively short tREC with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to dropouts would be required. Design information for guard time adjustment is shown in Figure 5.
Power-down and Inhibit Mode ( -02 only)
A logic high applied to pin 6 (PD) will place the device into standby mode to minimize power consumption. It stops the oscillator and the functioning of the filters. On the M-8870-01 models, this pin is tied to ground (logic low). Inhibit mode is enabled by a logic high input to pin 5 (INH). It inhibits the detection of 1633 Hz. The output code will remain the same as the previous detected code (see Table 1). On the M-8870-01 models, this pin is tied to ground (logic low).
Input Configuration
The input arrangement of the M-8870 provides a differential input operational amplifier as well as a bias source (VREF) to bias the inputs at mid-rail. Provision is made for connection of a feedback resistor to the op-amp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in Figure 4 with the op-amp connected for unity gain and VREF biasing the input at 1/2VDD. Figure 6 shows the differential configuration, which permits gain adjustment with the feedback resistor R5.
DTMF Clock Circuit
The internal clock circuit is completed with the addition of a standard 3.579545 MHz television color burst crystal. The crystal can be connected to a single M-8870 as shown in Figure 4, or to a series of M-8870s. As illustrated in Figure 7, a single crystal can be used to connect a series of M-8870s by coupling the oscillator output of each M-8870 through a 30 pF capacitor to the oscillator input of the next M-8870. Figure 5 Guard Time Adjustment
Teltone Corporation, 22121-20th Avenue SE, Bothell, WA 98021-4408 U.S.A 40-406-00011, Rev. E
Phone: 800-426-3926 or 425-487-1515 Fax: 425-487-2288 E-mail: info@teltone.com Internet: www.teltone.com
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M-8870
Table 2 Absolute Maximum Ratings
Parameter Power supply voltage (VDD - VSS) Voltage on any pin Current on any pin Operating temperature Storage temperature Symbol VDD VDC IDD TA TS Value 6.0 V max VSS -0.3, VDD +0.3 10 mA max -40C to + 85C -65C to + 150C
Note: Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied.
Table 3 DC Characteristics
Parameter Operating supply voltage Operating supply current Standby supply current (see Note 3) Power consumption Low level input voltage High level input voltage Input leakage current Pullup (source) current on OE Input impedance, signal inputs 1, 2 Symbol VDD IDD IDDQ PO VIL VIH IIH/IIL ISO RIN 8 Min 4.75 3.0 15 3.5 0.1 6.5 10 15.0 Typ* Max 5.25 7.0 100 35 1.5 Units V mA A mW V V A A m V V V mA mA V Test Conditions
PD=VDD f = 3.579 MHz, VDD = 5.0 V
VIN = VSS or VDD (see Note 2) OE = 0 V @ 1 kHz
VTSt 2.2 2.5 Steering threshold voltage VOL 0.03 No load Low level output voltage VOH 4.97 No load High level output voltage IOL 1.0 2.5 VOUT = 0.4 V Output low (sink) current 0.4 0.8 VOUT = 4.6 V IOH Output high (source) current VREF 2.4 2.7 No load Output voltage VREF ROR 10 Output resistance VREF k *Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Notes: 1. All voltages referenced to VSS unless otherwise noted. For typical values, VDD = 5.0V, VSS = 0V, TA = 25C. 2. Input pins defined as IN+, IN-, or OE. 3. -02 only.
Table 4 Operating Characteristics - Gain Setting Amplifier
Parameter Input leakage current Input resistance Input offset voltage Power supply rejection Common mode rejection DC open loop voltage gain Open loop unity gain bandwidth Output voltage swing Tolerable capacitive load (GS) Tolerable resistive load (GS) Symbol IN RIN VOS PSRR CMRR AVOL fC VO CL RL 50 55 60 1.2 3.5 4 25 Min Typ* 100 Max Units nA M mV dB dB dB MHz VP-P 100 50 pF No load 1 KHz -3.0V < VIN < 3.0V Test Conditions VSS < VIN < VDD
1.5
RL 100 K to VSS
k VCM 2.5 V P-P Common mode range *Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Note: 1. All voltages referenced to VSS unless otherwise noted. For typical values VDD = 5.0 V, VSS = 0 V, TA = 25C.
Teltone Corporation, 22121-20th Avenue SE, Bothell, WA 98021-4408 U.S.A 40-406-00011, Rev. E
Phone: 800-426-3926 or 425-487-1515 Fax: 425-487-2288 E-mail: info@teltone.com Internet: www.teltone.com
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M-8870
Table 5 Tone Decoding
FLOW FHIGH Key (ref.) OE H H H H H H H H H H H H H H H H L Q4 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Z Q3 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Z Q2 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Z Q1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Z
697 1209 1 697 1336 2 697 1477 3 770 1209 4 770 1336 5 770 1477 6 852 1209 7 852 1336 8 852 1477 9 941 1336 0 941 1209 F 941 1477 # 697 1633 A 770 1633 B 852 1633 C 941 1633 D ANY ANY ANY L = logic low, H = logic high, Z = high impedance
Figure 7 Common Crystal Connection
Figure 6 Differential Input Configuration Ordering Information M-8870-01 18-pin plastic DIP M-8870-01SM 18-pin plastic SOIC M-8870-01SMTR 18-pin plastic SOIC, tape and reel M-8870-02P 18-pin plastic DIP, power-down option M-8870-02S 18-pin plastic SOIC, power-down option M-8870-02T 18-pin plastic SOIC, power-down option, tape and reel
Teltone Corporation, 22121-20th Avenue SE, Bothell, WA 98021-4408 U.S.A 40-406-00011, Rev. E
Phone: 800-426-3926 or 425-487-1515 Fax: 425-487-2288 E-mail: info@teltone.com Internet: www.teltone.com
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M-8870
Table 6 AC Specifications
Parameter Valid input signal levels (each tone of composite signal) Positive twist accept Negative twist accept Frequency deviation accept limit Frequency deviation reject limit Third tone tolerance Noise tolerance Dial tone tolerance Tone present detection time Tone absent detection time Minimum tone duration accept Maximum tone duration reject Minimum interdigit pause accept Maximum interdigit pause reject Propagation delay (St to Q) Propagation delay (St to StD) Output data setup (Q to StD) Propagation delay (OE to Q), enable Propagation delay (OE to Q), disable Crystal clock frequency Clock output (OSC2), capacitive load Symbol Min -29 27.5 Typ* Max Units Notes 1,2,3,4,5,8 2,3,4,8 2,3,5,8,10 2,3,5 2,3,4,5,8,9,13,14 2,3,4,5,6,8,9 2,3,4,5,7,8,9 See Figure 8
3.5% -25 +18 5 0.5 20
+1 dBm 869 mVRMS 10 dB 10 dB 1.5% + 2 Hz Nom. Nom. -16 -12 +22 8 3 dB dB dB ms ms ms ms ms ms s s ms ns ns MHz pF
tDP tDA tREC tREC tID tDO tPQ tPStD tQStD tPTE tPTD fCLK CLO
14 8.5 40 40
User adjustable (see Figures 3 and 5)
20 6 9 4.0 50 300 3.5795 60 3.5831 30 11 16
OE = VDD
RL = 10 k, CL = 50 pF
3.5759
All voltages referenced to VSS unless otherwise noted. For typical values VDD = 5.0 V, VSS = 0 V, TA = 25C, fCLK = 3.579545 MHz. *Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Notes: 1. dBm = decibels above or below a reference power of 1 mW into a 600 W load. 2. Digit sequence consists of all 16 DTMF tones. 3. Tone duration = 40 ms. Tone pause = 40 ms. 4. Nominal DTMF frequencies are used, measured at GS. 5. Both tones in the composite signal have an equal amplitude. 6. Bandwidth limited (0 to 3 kHz) Gaussian noise. 7. The precise dial tone frequencies are (350 and 440 Hz) 2%. 8. For an error rate of better than 1 in 10,000. 9. Referenced to lowest level frequency component in DTMF signal. 10. Minimum signal acceptance level is measured with specified maximum frequency deviation. 11. Input pins defined as IN+, IN-, and OE. 12. External voltage source used to bias VREF. 13. This parameter also applies to a third tone injected onto the power supply. 14. Referenced to Figure 4. Input DTMF tone level at -28 dBm.
Teltone Corporation, 22121-20th Avenue SE, Bothell, WA 98021-4408 U.S.A 40-406-00011, Rev. E
Phone: 800-426-3926 or 425-487-1515 Fax: 425-487-2288 E-mail: info@teltone.com Internet: www.teltone.com
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M-8870
Explanation of Events (A) Tone bursts detected, tone duration invalid, outputs not updated. (B) Tone #n detected, tone duration valid, tone decoded and latched in outputs. (C) End of tone #n detected, tone absent duration valid, outputs remain latched until next valid tone. (D) Outputs switched to high impedance state. (E) Tone #n + 1 detected, tone duration valid, tone decoded and latched in outputs (currently high impedance). (F) Acceptable dropout of tone #n + 1, tone absent duration invalid, outputs remain latched. (G) End of tone #n + 1 detected, tone absent duration valid, outputs remain latched until next valid tone. Explanation of Symbols VIN ESt St/GT Q1 - Q4 StD OE tREC tREC tID tDO tDP tDA TGTP TGTA DTMF composite input signal. Early steering output. Indicates detection of valid tone frequencies. Steering input/guard time output. Drives external RC timing circuit. 4-bit decoded tone output. Delayed steering output. Indicates that valid frequencies have been present/absent for the required guard time, thus constituting a valid signal. Output enable (input). A low level shifts Q1 - Q4 to its high impedance state. Maximum DTMF signal duration not detected as valid. Minimum DTMF signal duration required for valid recognition. Minimum time between valid DTMF signals. Maximum allowable dropout during valid DTMF signal. Time to detect the presence of valid DTMF signals. Time to detect the absence of valid DTMF signals. Guard time, tone present. Guard time, tone absent.
Figure 8 Timing Diagram
Teltone Corporation, 22121-20th Avenue SE, Bothell, WA 98021-4408 U.S.A 40-406-00011, Rev. E
Phone: 800-426-3926 or 425-487-1515 Fax: 425-487-2288 E-mail: info@teltone.com Internet: www.teltone.com
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M-8870
A A1 b b2 C D E E1 e ec L
Tolerances Inches Metric (mm) Min Max Min Max .210 5.33 .015 .38 .014 .022 .36 .56 .045 .070 1.1 1.7 .008 .014 .20 .36 .880 .920 23.35 23.37 .300 .325 7.62 8.26 .240 .280 6.10 7.11 .100 BSC 2.54 BSC 15 0 15 0 .115 .150 2.92 3.81
A A1 b D E e H L
Tolerances Inches Min Max .0926 .1043 .0040 .0118 .013 .020 .4469 .4625 .2914 .2992 .050 BSC .394 .419 .016 .050
Metric (mm) Min Max 2.35 2.65 .10 .30 .33 .51 11.35 11.75 7.4 7.6 1.27 BSC 10.00 10.65 .40 1.27
.
Figure 9 Package Dimensions
Teltone Corporation, 22121-20th Avenue SE, Bothell, WA 98021-4408 U.S.A 40-406-00011, Rev. E
Phone: 800-426-3926 or 425-487-1515 Fax: 425-487-2288 E-mail: info@teltone.com Internet: www.teltone.com
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